Typically, as the degree of integration in semiconductor devices advances, the number of metallic interconnects increases, but the pitch of the metallic interconnects decreases. The diminution of the pitch increases the resistance of the metallic interconnects. Moreover, a metallic interconnect adjacent an interlayer dielectric layer (hereinafter referred to as an “ILD”) may form a parasitic capacitor structure which degrades the characteristics of the associated semiconductor device. For example, the RC constant, (which determines the response time of the semiconductor device), and the power consumption of the semiconductor device may be increased by this parasitic capacitance.
One obvious solution to these problems is to employ an ILD with a low dielectric constant to manufacture highly integrated semiconductor devices. To this end, a fluorine doped silicate glass (hereinafter referred to as “FSG”) layer, is often used as the ILD because it has a low dielectric constant. The dielectric constant of the FSG layer varies with the concentration of fluorine in the FSG layer. For example, the dielectric constant of the FSG layer increases as the concentration of fluorine increases. However, when the concentration of fluorine is high, the fluorine of the FSG layer is easily coupled with moisture; thereby causing corrosion of the metallic interconnect(s). Due to this trade-off, an FSG layer having a relatively high dielectric constant (e.g., about 3.5) is typically used.
FIG. 1 is a cross-sectional view illustrating a conventional semiconductor device. Referring to FIG. 1, metallic interconnects 12 are formed over a substrate 11 which may include, for example, active devices. A barrier layer 13 is deposited on the substrate 11 and interconnects 12. Subsequently, an FSG layer 14 including fluorine is formed as an ILD on the barrier layer 13. A diffusion protective layer 15 is then deposited on the FSG layer 14. The barrier layer 13 prevents damage to the metallic interconnects 12. The diffusion protective layer 15 prevents diffusion of the fluorine of the FSG layer 14 into adjacent layers. Both the barrier layer 13 and the FSG layer 14 are made of undoped silicate glass.
However, the conventional ILD fabrication method described above requires an extended time to complete because at least two separate apparatus are used to form the FSG layer 14, the barrier layer 13, and the diffusion protective layer 15.
Hsiao et al., U.S. Pat. No. 6,303,519, describes a method of forming a fluorinated silicon oxide layer or an FSG film having a dielectric constant less than 3.2. The method described in Hsiao et al. supplies a fluorine-rich gas and an oxygen-rich gas into a reacting chamber, and creates a plasma environment in the reacting chamber. The flow rate of the oxygen-rich gas is adjusted until the ratio of the flow rate of the oxygen-rich gas to the total flow rate of the fluorine-rich gas and a silicon-rich gas is less than or equal to a pre-selected value to form the FSG film.
Cha et al., U.S. Pat. No. 6,376,360, describes a method of forming metal structures, encapsulated in silicon rich oxide (hereinafter referred to as “SRO”) to protect the metal structures from the corrosive effects of fluorine radicals.
Liu et al., U.S. Pat. No. 6,586,347, describes an improved composite dielectric structure and method of forming the same which prevents delamination of FSG (F-doped SiO2), and allows FSG to be used as the inter-level dielectric between successive conducting interconnection patterns in multilevel integrated circuit structures.